1. Technology Field
The present invention relates to a memory management method for managing a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same.
2. Description of Related Art
Digital cameras, cell phones, and MP3 players have undergone rapid growth in recent years, so that consumers' demands for storage media have also increased drastically. Since a rewritable non-volatile memory has the characteristics of non-volatility of data, low power consumption, small volume, non-mechanical structure, and fast reading and writing speed, the rewritable non-volatile memory is the most adaptable memory to be applied in a portable electronic product, e.g., a notebook computer. A solid state drive (SSD) is a storage apparatus which utilizes a flash memory as its storage medium. Therefore, the flash memory industry has become a very popular part of the electronic industry in recent years.
In a NAND flash memory, memory cells are linked through bit lines and word lines to form a memory cell array. At present, the NAND flash memory may be classified into a multi-level cell (MLC) NAND flash memory and a single-level cell (SLC) NAND flash memory according to the number of bits which may be stored in each memory cell. Each memory cell can store one bit of data in the SLC NAND flash memory, and each memory cell can store at least two bits of data in the MLC NAND flash memory. For instance, in an exemplary 4-level cell NAND flash memory, each memory cell may store 2 bits of data (i.e., “11,” “10,” “00,” or “01”).
FIG. 1 is a schematic diagram illustrating a flash memory device according to the related art.
With reference to FIG. 1, a flash memory device 1 includes a charge-trapping layer 2 for storing electrons, a control gate 3 for applying a bias voltage, a tunnel oxide layer 4, and an interpoly dielectric layer 5. When it is intended to write data into the flash memory device 1, a threshold voltage of the flash memory device 1 may be changed by injecting electrons into the charge-trapping layer 2. Accordingly, a digital-level state of the flash memory device 1 is defined to implement a function of storing data. Here, the process of injecting the electrons to the charge-trapping layer 2 is referred to as a programming process. By contrast, when it is intended to remove the stored data, the injected electrons are removed from the charge-trapping layer 2, and thereby the flash memory device 1 is restored back to the default state before programming.
During writing and erasing operations, the flash memory device 1 deteriorates due to the frequent injection and removal of the electrons, thus increasing the speed of writing the electrons and extending the distribution of the threshold voltage. As a result, after the flash memory device 1 is programmed, the storage state of the flash memory device 1 is unlikely to be identified accurately, which results in the occurrence of error bits. How to effectively learn the aging degree of the flash memory device and correspondingly adjust a mechanism of operating the flash memory device is one of the major subjects to which people skilled in the art are dedicated.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.